1. Technical Field
The present invention relates to a wafer unit for testing and a test system equipped with the wafer unit for testing. In particular, the present invention relates to a wafer unit for testing, which includes a temperature distribution adjusting section for adjusting the temperature distribution of a semiconductor wafer on which a plurality of semiconductor chips are formed, and to a test system equipped with the wafer unit for testing.
2. Related Art
An apparatus is already known to conduct a test to a semiconductor wafer in which a plurality of semiconductor chips are formed to test pass/fail of each semiconductor chip (see Patent Document No. 1 for example). Such an apparatus can have a probe card that can be collectively electrically connected to a plurality of semiconductor chips. With such an apparatus, a plurality of semiconductor chips can be simultaneously tested.    Patent Document No. 1: Japanese Patent Application Publication No. 2002-222839
When a test is simultaneously conducted to a plurality of semiconductor chips, when a semiconductor chip has experienced an excessive current, the particular semiconductor chip may experience increased temperature, which tend to more or less increase the temperature of the semiconductor chips positioned near the particular semiconductor chip. This prevents the semiconductor chips near the particular semiconductor chip having caused excessive current, from being tested under the same temperature condition as that of the other semiconductor chips.